spt7750 8-bit, 500 msps flash a/d converter block diagram 256 255 152 151 128 127 64 63 2 1 clock buffer 256 to 8 bit decoder with metastable error correction do (lsb) d1 d2 d3 d4 d5 d6 d7 (msb) d8 (ovr) v rt analog input preamp comparator v rm v rb clk clk demux clock buffer d8b d7b ? ? d5b ? ? d2b d1b d0b d8a d7a ? ? ? d5a ? ? ? d2a d1a d0a 1:2 demultiplexer ecl output buffers and latches drb (data ready) drb (data ready) d8b (ovr) d7b (msb) d6b d5b d4b d3b d2b d1b d0b (lsb) dra (data ready) dra (data ready) d8a (ovr) d7a (msb) d6a d5a d4a d3a d2a d1a d0a (lsb) bank b bank a signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 general description applications ? digital oscilloscopes ? transient capture ? radar, ew, ecm ? direct rf down-conversion features ? 1:2 demuxed ecl compatible outputs ? wide input bandwidth - 900 mhz ? low input capacitance - 15 pf (mquad) ? metastable errors reduced to 1 lsb ? monolithic for low cost ? gray code output the spt7750 is a full parallel (flash) analog-to-digital con- verter capable of digitizing full scale (0 to -2 v) inputs into eight-bit digital words at an update rate of 500 msps. the ecl-compatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. the spt7750's wide input bandwidth and low capacitance eliminate the need for exter- nal track-and-hold amplifiers for most applications. a propri- etary decoding scheme reduces metastable errors to the 1 lsb level. the spt7750 operates from a single -5.2 v supply, with a nominal power dissipation of 5.5 w. the spt7750 is available in an 80l surface-mount mquad package over the industrial temperature range and in die form. contact the factory for availability of /883 versions.
spt 2 3/5/97 spt7750 electrical specifications t j = t c = t a = +25 c , v ee =-5.2 v, v rb =-2.00 v, v rm =-1.0 v, v rt =0.00 v, f clk =500 mhz, duty cycle=50%, unless otherwise specified. test test spt7750a spt7750b parameters conditions level min typ max min typ max units resolution 8 8 bits dc accuracy integral nonlinearity f clk = 100 khz i -1.0 +1.0 -1.5 +1.5 lsb differential nonlinearity f clk = 100 khz i -0.85 +0.95 -0.95 +1.5 lsb no missing codes guaranteed guaranteed analog input input voltage range i v rb v rt v rb v rt v input bias current v in =0 v i .75 2.0 .75 2.0 ma input resistance v 15 15 k w input capacitance over full input range v 15 15 pf input bandwidth small signal v 900 900 mhz large signal v 500 500 mhz offset error v rt iv -30 +30 -30 +30 mv offset error v rb iv -30 +30 -30 +30 mv input slew rate v 5 5 v/ns clock synchronous input currents v 2 2 m a reference input ladder resistance i 60 80 60 80 w reference bandwidth v 30 30 mhz timing characteristics maximum sample rate i 500 500 mhz aperture jitter v 2 2 ps acquisition time v 250 250 ps clk to data ready delay iv 0.9 1.4 1.9 0.9 1.4 1.9 ns clock to data delay iv 1.25 1.75 2.25 1.25 1.75 2.25 ns dynamic performance signal-to-noise ratio (without harmonics) f in = 50 mhz i 47 45 db f in = 250 mhz i 44 42 db total harmonic distortion f in = 50 mhz i -46 -44 dbc f in = 250 mhz i -38 -36 dbc notes: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied condi- tions in typical applications. absolute maximum ratings (beyond which damage may occur) 1 25 c output digital output current ........................................ 0 to -28 ma temperature operating temperature, ambient ...................... .-25 to +85 c case ................................... +125 c junction ............................... +150 c lead temperature, (soldering 10 seconds). ............. +300 c storage temperature ...................................... -65 to +150 c supply voltages negative supply voltage (v ee to gnd) ......... .-7.0 to +0.5 v ground voltage differential ............................. .-0.5 to +0.5 v input voltage analog input voltage ........................................ +0.5 v to v ee reference input voltage .................................. +0.5 v to v ee digital input voltage ......................................... +0.5 v to v ee reference current v rt to v rb .................................... 35 ma
spt 3 3/5/97 spt7750 electrical specifications t j = t c = t a = +25 c , v ee =-5.2 v, v rb =-2.00 v, v rm =-1.0 v, v rt =0.00 v, f clk =500 mhz, duty cycle=50%, unless otherwise specified. test test spt7750a spt7750b parameters conditions level min typ max min typ max units dynamic performance signal-to-noise and distortion f in = 50 mhz i 43 41 db f in = 250 mhz i 37 35 db spurious free dynamic range f in = 50 mhz i 49 44 db f in = 250 mhz i 41 36 db digital inputs input high voltage (clk, nclk) i -1.1 -0.7 -1.1 -0.7 v input low voltage (clk, nclk) i -1.8 -1.5 -1.8 -1.5 v clock pulse width high (t pwh ) i 1.0 0.67 1.0 0.67 ns clock pulse width low (t pwl ) i 1.0 0.67 1.0 0.67 ns digital outputs logic 1 voltage i -1.1 -0.9 -1.1 -0.9 v logic 0 voltage i -1.8 -1.5 -1.8 -1.5 v rise time 20% to 80% v 450 450 ps fall time 20% to 80% v 450 450 ps power supply requirements voltage v ee iv -4.95 -5.2 -5.45 -4.95 -5.2 -5.45 v current i ee i 1.05 1.2 1.05 1.2 a power dissipation i 5.5 6.25 5.5 6.25 w typical thermal impedance: q jc = +4 c/w. test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. unless otherwise noted, all tests are pulsed tests; therefore, t j = t c = t a . test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range.
spt 4 3/5/97 spt7750 general description the spt7750 is one of the fastest monolithic 8-bit parallel flash a/d converters available today. the nominal conver- sion rate is 500 msps and the analog bandwidth is in excess of 900 mhz. a major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block dia- gram). this not only reduces clock transient kickback to the input and reference ladder due to a low ac beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. the preamplifiers act as buffers and stabilize the input capaci- tance so that it remains constant over different input voltage figure 1 - spt7750 typical interface circuit and frequency ranges and therefore makes the part easier to drive than previous flash converters. the preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to "trip" into or out of the active state. this gain reduces metastable states that can cause errors at the output. the spt7750 has true differential analog and digital data paths from the preamplifiers to the output buffers (current mode logic) for reducing potential missing codes while rejecting common mode noise. signature errors are also reduced by careful layout of the analog circuitry. the output drive capability of the device can provide full ecl swings into 50 w loads. 50 w 50 w v in v in v rtf v rts * u1 + - 22 w * u1 + - 22 w -5.2 v 2n2907 v rbs v rbf 50 w v in -2.0 v reference convert u2 50 w -2 v pulldown (analog) clk nclk -5.2 v v ee agnd dgnd v rm drb (data ready) drb (data ready) d8b (ovr) d7b (msb) d6b d5b d4b d3b d2b d1b d0b (lsb) dra (data ready) dra (data ready) d8a (ovr) d7a (msb) d6a d5a d4a d3a d2a d1a d0a (lsb) bank b bank a -2.0 v pulldown (digital) 50 w .1 f fb = ferrite bead u1 = op291 or equivalent with low offset/noise. r = 1 k w ; 0.1% matched. = agnd = dgnd u2 = motorola eclinps lite, mc10el16, differential receiver with 250 ps (typ) propagation delay. * = 10 f tantalum capacitor and 0.1 f chip capacitor ** = care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver. r r * -5.2 v fb **
spt 5 3/5/97 spt7750 (v rm ) and agnd (v rt force and sense). the reference pins and tap can be driven by op amps as shown in figure 1 or v rm may be bypassed for limited temperature operation. these voltage inputs can be bypassed to agnd for further noise suppression if so desired. table i - output coding v in > -0.5 lsb -0.5 lsb -1.5 lsb ? -1.0 v -2.0 v+ 1/2 lsb < (-2.0 v + 1/2 lsb) d8 1 1 0 0 0 ? 0 0 ? 0 0 0 d7 ?? ?? ?0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indicates the transition between the two codes thermal management the typical thermal impedance is as follows: q ca = +17 c/w in still air with no heat sink we highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. we have found that a thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under labo- ratory tests. application specific conditions should be taken into account to ensure that the device is properly heat sinked. typical interface circuit the circuit in figure 1 is intended to show the most elaborate method of achieving the least error by correcting for integral linearity, input induced distortion and power supply/ground noise. this is achieved by the use of external reference ladder tap connections, input buffer and supply decoupling. please contact the factory for the spt7750 evaluation board applications note that contains more details on interfacing the spt7750. the function of each pin and external connections to other components is as follows: v ee , agnd, dgnd v ee is the supply pin with agnd as ground for the device. the power supply pins should be bypassed as close to the device as possible with at least a .01 m f ceramic capacitor. a 1 m f tantalum can also be used for low frequency suppression. dgnd is the ground for the ecl outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 5. v in (analog input) there are two analog input pins that are tied to the same point internally. either one may be used as an analog input sense and the other for input force. this is convenient for testing the source signal to see if there is sufficient drive capability. the pins can also be tied together and driven by the same source. the spt7750 is superior to similar devices due to a pream- plifier stage before the comparators. this makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. clk, clk (clock inputs) the clock inputs are designed to be driven differentially with ecl levels. the duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. if this is not important to the intended application, then duty cycles other than 50% may be used. d0 to d8, dr, ndr, (a and b) the digital outputs can drive 50 w to ecl levels when pulled down to -2 v. when pulled down to -5.2 v, the outputs can drive 130 w to 1 k w loads. all digital outputs are grey code with the coding as shown in table 1. v rbf , v rbs , v rtf , v rts , v rm (reference inputs) there are two reference inputs and one external reference voltage tap. these are -2 v (v rb force and sense), mid-tap
spt 6 3/5/97 spt7750 figure 2 - timing diagram input circuit output circuit clock input figure 3 - subcircuit schematics agnd clk v ee clk agnd data out dgnd agnd v in v ee v r v in clk nclk dra ndra drb ndrb data bank b n-1 n+1 n+3 n n+1 n+2 n+3 n+4 n+5 n+6 n-2 n n+2 n+4 1.4 ns typ 1.75 ns typ data bank a 2.0 ns 1.4 ns typ 1.75 ns typ are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to v rt (0 v), down to the point where the magnitude of the input signal changes sign (thermometer code). the output of each comparator is then registered into four 64-to-6 bit decoders when the clk is changed from high to low. at the output of the decoders is a set of four 7-bit latches which are enabled ("track") when the clock changes from high to low. from here, the output of the latches are coded into 6 lsbs from 4 columns and 4 columns are coded into 2 msbs. finally, 8 ecl output latches and buffers are used to drive the external loads. the conversion takes one clock cycle from the input to the data outputs. operation the spt7750 has 256 preamp/comparator pairs which are each supplied with the voltage from v rt to v rb divided equally by the resistive ladder as shown in the block diagram. this voltage is applied to the positive input of each preampli- fier/comparator pair. an analog input voltage applied at v in is connected to the negative inputs of each preamplifier/com- parator pair. the comparators are then clocked through each one's individual clock buffer. when the clk pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. when the clk pin changes from low to high the comparators
spt 7 3/5/97 spt7750 package outline 80-pin mquad b f h i k a c d e j g l m inches millimeters symbol min max min max a 0.937 0.945 23.80 24.00 b 0.777 0.785 19.72 19.93 c 0.472 typ 12.0 typ d 0.541 0.549 13.73 13.94 e 0.701 0.709 17.80 18.00 f 0.032 typ 0.80 typ g 0.014 typ 0.36 typ h 0.114 0.122 2.90 3.10 i .006 typ 0.15 typ j 0.724 typ 18.4 typ k 0.099 0.109 2.51 2.77 l7 7 m 0.026 0.036 0.66 0.91
spt 8 3/5/97 spt7750 pin assignments ordering information part number description temperature range package type SPT7750AIK inl = 1.0 lsb -25 to +85 c 80l mquad spt7750bik inl = 1.5 lsb -25 to +85 c 80l mquad spt7750bcu inl = 1.5 lsb +25 c die* dgnd d2b d3b d4b v ee v ee d5b dgnd d6b dgnd d7b d8b n/c n/c agnd agnd agnd agnd v ee v ee v rbf v ee v ee v rbs 1 1 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 54 64 63 62 61 60 59 58 57 56 55 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 dgnd n/c n/c d3a d2a v ee d1a dgnd d a dgnd ndra dra agnd agnd clk v ee nclk v ee v ee agnd agnd v rts v rtf n/c v ee v ee v ee agnd agnd v rm n/c v in v in n/c agnd agnd v ee v ee agnd agnd v ee d4a d5a d6a dgnd d7a dgnd d8a dgnd ndrb dgnd drb dgnd d b v ee d1b mquad pin functions name function v ee negative supply nominally -5.2 v agnd analog ground v rtf reference voltage force top, nominally 0 v v rts reference voltage sense top v rm reference voltage middle, nominally -1 v v rbf reference voltage force bottom, nominally -2 v v rbs reference voltage sense bottom v in analog input voltage, can be either voltage or sense dgnd digital ground d0-d7a data output bank a d0-d7b data output bank b dra data ready bank a ndra not data ready bank a drb data ready bank b ndrb not data ready bank b d8a overrange output bank a d8b overrange output bank b clk clock input nclk clock input *please see the die specification for guaranteed electrical performance. signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is hereby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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